1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly, the present invention relates to page buffer circuits and other circuits utilized in non-volatile semiconductor memory devices.
2. Description of the Related Art
The demand for electrically programmable and electrically erasable nonvolatile memory devices has increased dramatically in recent years. Such devices are at least partially characterized by the ability to maintain stored data even in the absence of supplied power. The use of so-called flash memories has become especially popular, particularly, but not exclusively, in the context of portable devices such as digital cameras, cell phones, personal data assistants (PDAs), and laptop computers. Flash memories, such as NAND-type flash memories, are capable of storing large amounts of data in a relatively small area.
As background discussion, the basic operating principles underlying flash memory cells and flash memory devices are presented below. However, it should be clearly understood that the discussion that follows is merely exemplary and does not in any way limit and/or define the scope of the present invention.
The operating principle of a flash memory cell will be described first with reference to FIGS. 1A through 1C. FIG. 1A illustrates a typical configuration in which a flash memory cell transistor is connected to word and bit lines of a memory device, FIG. 1B shows the circuit symbol of a flash memory cell transistor, and FIG. 1C shows the threshold voltage characteristics of a flash memory cell transistor.
Referring collectively to FIGS. 1A through 1C, a flash memory cell transistor includes a source region 4 and a drain region 5 located at the surface of a substrate 3. In this example, the substrate is P-type, and the source and drain regions 4 and 5 are N+-type. A gate structure is aligned over a channel region defined between the source and drain regions 4 and 5. The gate structure includes a floating gate 1 and a control gate 2. Although not shown, a tunneling dielectric layer is interposed between the floating gate 1 and surface of the substrate Psub, and another thin oxide layer (or control dielectric) is interposed between the floating gate 1 and the control gate 2. In the illustrated example, the drain voltage Vd is supplied from a bit line BL, the control gate voltage Vcg is supplied from a word line WL, and the source voltage Vs is connected to a reference potential such as ground.
The threshold voltage of the flash memory cell transistor defines its stored logic value. That is, when the flash memory cell transistor is in its initial state (also called an “erased” state), the threshold voltage Vth is relatively low as shown in FIG. 1C. In this state, the cell transistor is designated to have a logic value “1”, which generally corresponds to the ON state of a conventional transistor device. On the other hand, when the cell transistor is in its “programmed” state (PGM), the threshold voltage Vth is relatively high. This high threshold state is designated to have a logic value “0”, which generally corresponds to the OFF state of a conventional transistor device.
In order to change (program) the cell transistor from its initial state to its programmed state, a process known as Fowler-Nordheim (FN) tunneling is utilized. Briefly, a relatively large positive potential difference is created between the control gate 2 and the substrate Psub, and excited electrons within the channel on the surface of the substrate Psub are caused to be pushed through and trapped in the floating gate 1. These negatively charged electrons act as a barrier between the control gate 2 and the channel on the substrate Psub, thus increasing the threshold voltage of the cell transistor as represented in FIG. 1C. The cell transistor can be brought back to its initial state by forming a large negative potential difference between the control gate 2 and the substrate Psub, whereby resultant FN tunneling draws the trapped electrons back across the thin oxide layer between the floating gate 1 and substrate Psub, thus removing the electron barrier and decreasing the threshold voltage Vth.
Turning now to FIG. 2, the ON and OFF threshold voltages Vth of the large numbers of flash cell transistors found in flash memory devices generally exhibit bell curve distributions. For example, the threshold voltages Vth of the erased cell transistors (having logic value “1”) may be distributed between −3v and −1v, whereas the threshold voltages Vth of the programmed cell transistors (having logic value “0”) may be distributed between +1v and +3v.
Referring now to FIG. 3A, NAND flash memories are characterized by serially connected “strings” 6 of flash memory cell transistors, where multiple parallel strings 6 constitute a memory block 7 of the flash memory. As shown, each string 6 is comprised of a plurality of flash memory cell transistors connected in series along a bit line B/L in the memory block 7. Word lines W/L are connected to the control gates of each respective row of cell transistors in the memory block 7. For example, a flash memory device may contain 16 or 32 cell transistors in each string 6, and 4224 strings (B/L0 . . . B/L4223) in each memory block 7.
At opposite ends of each string 6 are string select transistors having control gates which receive a string select signals SSL and a ground select signal GSL. Generally, the select signals SSL and GSL are utilized in reading and programming of the cell transistors. Further, at the end of each string is a common source line CSL which sets a source line voltage of the cell transistor strings 6 of each memory block 7.
The table of FIG. 3B generally shows the various voltage conditions of the signals illustrated in FIG. 3A for each of erase, program and read operations. In this table, “Sel. W/L” denotes the selected word line for which the program or read operation is to be executed, and “Unsel. W/L” denotes the remaining word lines of the memory block. For the erase operation, “Sel. W/L denotes the word lines of the selected memory block for which the erase operation is to be executed, and “Unsel. W/L denotes the word lines of the remaining memory blocks in the memory cell array.
A NAND flash programming operation will now be described with reference to FIGS. 3B and 4. Here, string select signal SSL is set to VDD, ground select signal GSL is set to 0v, the common source line CSL voltage is set to between VSS and VDD (e.g. 1.5v), and the bulk voltage is set to 0v. Generally, programming occurs one word line at a time, and accordingly, one word line is selected per memory block for each programming operation. Here, the selected word line W/L receives a programming voltage Vpgm, while the remaining unselected word lines W/L receive a voltage Vpass, where Vpgm is greater than Vpass. Vpgm is of a sufficiently high voltage (e.g., 18v) that FN tunneling results when the bit line B/L voltage of any cell transistor of the selected word line is 0v. In other words, when the bit line B/L voltage of any cell transistor of the selected word line is 0v, the program voltage Vpgm creates a voltage difference (e.g., 18v) which is sufficient to initiate FN tunneling, thus placing the cell transistor in a programmed state. On the other hand, when the bit line B/L voltage of any cell transistor is VDD, FN tunneling is inhibited as a result of insufficient voltage difference (e.g., 10v). As such, the cell is said to be “program inhibited”. In the meantime, the pass voltage Vpass is sufficiently high to place the non-selected cell transistors in a conductive state, but not so high as to cause FN tunneling.
Referring to FIGS. 3B and 5, a read operation will now be described. In this case, string select signal SSL is set to Vread, ground select signal GSL is set to Vread, the common source line CSL voltage is set to 0v, and the bulk voltage is set to 0v. As with programming, the read operation typically occurs one word line at a time, and accordingly, one word line is selected per memory block for each read operation. Here, the selected word line W/L is set to 0v, while the remaining unselected word lines W/L receive a read voltage Vread. In this example, Vread is 4.5v, which exceeds the threshold voltage distributions of the “1” and “0” cell transistors. Therefore, the cell transistors coupled to the non-selected word lines become conductive. On the other hand, the 0v voltage applied to the selected word line falls between the threshold voltage distributions of the “1” and “0” cell transistors. As such, only the “1” cell transistors connected to the selected word line become conductive, whereas the remaining cell transistors of the selected word line are nonconductive. The result is a voltage difference among the bit lines B/L of the memory block. In the example given in the table of FIG. 3B, a bit line B/L voltage of about 1.2v is read as having a “0” state cell transistor at the selected word line, and a bit line voltage of less than 0.8v is read as having a “1” state cell transistor at the selected word line.
Referring to FIGS. 3B and 6, an erase operation will now be described. In this case, the bit lines B/L, string select signal SSL, ground select signal GSL, common source line CSL, and the word lines of the unselected memory blocks are all set to a floating state. On the other hand, the selected word line voltage is set to 0v, and the bulk voltage is set to Verase (e.g., 19-21v). As such, a negative voltage difference is formed between the control gate and the bulk, resulting in FN tunneling across the gate oxide between the floating gate and the substrate. As a result, the threshold voltage distribution is reduced from the programmed “0” state to the erased “1” state. Note that all the cell transistors of the selected memory block are in the erased “1” state after the erase operation.
As previously mentioned, reading and programming of the memory block are executed one word line at a time within the memory block. In some applications, however, it is more accurate to say that these operations are executed “page by page” within the memory block. This concept is generally illustrated in FIG. 7. In the illustrated example, the bit lines BL <k:0> are divided into even and odd bit lines BL_E<k:0> and BL—0<k:0>. The cell transistors of each word line constitute pages of the memory block, and in the example of FIG. 7, each word line is connected to an odd page and an even page of the memory block. As will be explained in more below, the page buffers PB<k:0> contained in a page buffer block are utilized to transmit read data from, and program data to, the flash memory block. Generally, one page buffer PB is provided for each pair of odd and even bit lines.
FIG. 8 is a block diagram illustrating core elements of one example of a NAND-type flash memory, in which a so-called “Y-gating” technique is utilized to access bit lines of the memory. As shown, a plurality of page buffer blocks PBB <31:0> are connected via bit lines BL<255:0> to a memory cell array MCARR. Each page buffer block PBB interfaces with eight bit lines BL. Although not shown in FIG. 8, each bit line BL is actually constituted by a pair of odd and even bit lines as discussed previously in connection with FIG. 7.
A plurality of page buffer decoders PBDE <31:0> are operatively coupled to the respective page buffer blocks PBB <31:0>, y address lines Ya <7:0>, y address lines Yb <31:0>, and a global data bus GDB. As will be explained in more detail below, the y address lines Ya <7:0> are commonly applied to all of the page buffer decoders PBDE <31:0>, whereas individual ones of the y address lines Yb <31:0> are applied to the respective page buffer decoders PBDE <31:0>. In other words, page buffer decoder PBDE0 receives y addresses Ya <7:0> and Yb0, page buffer decoder PBDE1 receives y addresses Ya <7:0> and Yb1, and so on. Internal data lines IDB<255:0> are coupled between the page buffer blocks PBB <31:0> and page buffer decoders PBDE <31:0>. In the example of FIG. 8, eight internal data lines IDB are provided between each corresponding pair of page buffer block PBB and page buffer decoder PBDE.
Also applied to the page buffer blocks PBB <31:0> are data input selection signals DI and nDI, and latch signals LCH <7:0>, the functions of which are described below in connection with FIG. 9.
FIG. 9 is a schematic circuit diagram for explaining the page buffers PB and the page buffer decoders PBDE illustrated in FIG. 8. For convenience of explanation, FIG. 9 illustrates the page buffers PB<7:0> in a side-by-side arrangement (i.e., juxtaposed in the word line direction). In reality, however, the page buffers are stacked one over the other (i.e., juxtaposed in the bit line direction).
The page buffer decoder PBDE0 of FIG. 9 includes a first transistor connected between the global data bus GDB and a common internal data line IDBC, and a plurality of second transistors connected between the common internal data line and respective internal lines IDB <7:0> of the page buffers PB<7:0>. As shown, the gate of the first transistor receives the y address signal Yb0, while the respective gates of the second transistors receive the y address signals Ya <7:0>. It should thus be apparent that the y address Yb <31:0> is used to selected any one of the page buffer blocks PBB <31:0>, and the y address Ya <7:0> is used to select a bit line BL within the selected page buffer block PBB.
The page buffer PB0 includes a latch circuit having a latch node CMNLA and an inverted latch node CMNLAn. First and second transistors of the page buffer PB0 are respectively controlled by the data input selection signals DI and nDI, and these transistors are connected between internal data line IDB0 and the inverted latch node CMNLAn and latch node CMNLA, respectively. Another transistor is controlled by a page buffer select signal PBSLT, and is connected between the latch node CMNLA and a sense node NSEN0. The sense node NSEN0, which is connected to a memory cell string of the memory cell array, is selectively connected to voltage VDD by operation of another transistor which is controlled by a load control signal PLOAD. Finally, two more transistors are connected in series between the internal data line IDB and a reference voltage VSS. One of these two transistors is controlled by the voltage appearing on the sense node NSEN0, while the other is controlled by the latch signal LCH<0>.
Briefly, in a programming operation, the latch circuit of the page buffer PB0 stores a logic value as dictated by the data input selection signals DI and nDI and the voltage of the internal data line IDB, and this logic value (i.e., the voltage appearing on latch node CMNLA) is then transferred to the bit line of the memory cell string for programming. Likewise, in a reading operation, the sensed voltage appearing on the sense node NSEN0 is temporarily stored in the latch circuit, and then transferred to the global data bus GDB via the internal data line IDB. Note that the internal data line IDB functions as a shared input and output line.
Conventional non-volatile memory devices described above suffer from a number of drawbacks, particularly as the layout area of the various circuits is reduced as the memory devices become more integrated to meet demands for higher memory capacities. Without intending to provide an exhaustive listing, some examples of these drawbacks are discussed below.
Parasitic capacitive coupling between internal data lines can result as illustrated in FIG. 10. As mentioned previously, and as shown in FIG. 10, the page buffers <7:0> of each page buffer block PBB are juxtaposed (stacked) in the bit line direction, i.e., between the page buffer decoder PBDE and the memory cell array MCARR. Also illustrated are a number of transistors which are controlled by a sense node blocking signal SOBLK so as to selectively couple the sense nodes SON <7:0> to the bit lines BL<7:0>, respectively.
The internal data lines IDB of the respective page buffers PB all extend in parallel to each other within the page buffer block PBB. As the layout area of the page buffers PB is reduced, the pitch P between adjacent internal data lines IDB becomes smaller, and accordingly, capacitive coupling increases between adjacent internal data lines IDB. The resultant coupling noise between adjacent internal data lines IDB can cause signal distortion and data errors.
The large parasitic capacitance of the internal data lines IDB can also create a charge sharing condition with the low capacitive latch node of the latch circuit of each page buffer PB. In some cases, this can result in the data being flipped. Further, the heavy output load of the internal data lines IDB makes it necessary to increase the output drive capability of the page buffers, which can be problematic when space and power resources are limited.
Also, referring again to FIG. 8, the bus region of the illustrated example includes 40 y address lines. This relatively large number of lines must be attended by a large layout area for the bus region of the device, thus occupying scarce space resources.